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DD7-DD chip K134SP1 comparator Scheme of comparison (comparator) of two four-digit numbers. It has 11 entrances: four-digit numbers of A0-A3 and V0-V3, three entrances of I (A to B) are necessary for increase in capacity of the scheme (connection of several joint venture IS. The comparator has three exits: A B. Numbers of conclusions are specified on the schematic diagram 16 food; the 8-general;

Summation of binary-coded decimal numbers can be made by rules of usual binary arithmetics, and then to make binary-coded decimal correction. Binary-coded decimal correction consists in check of each tetrad on admissible codes. If in any tetrad the forbidden combination is found, it speaks about overflow. In this case it is necessary to make binary-coded decimal correction. Binary-coded decimal correction consists in additional summation of number six (number of the forbidden combinations) with a tetrad in which there was an overflow or there was a transfer in the senior tetrad. Let's give two examples:

xi, yi - the bits of the same name of numbers X and Y, ci - transfer from the previous category, si - the partial sum on the module two and c (i + - transfer in the following category. Values c (i + coincide with values of function of a mazhoritarnost therefore we will use the ready decision:

Operation (+) is called - the sum on the module two. The device realizing these rules is called as the one-digit half-adder and has two entrances and two exits. Addition of three one-digit numbers is made as follows:

The register 1534IR34 of a chip of DD1, DD Is two four-digit buffer registers. Each of registers has four entrances of data and four exits, an entrance dumping of R in a condition of logical zero, a conclusion of permission of an exit of EO an entrance of permission of record RE. Numbers of conclusions are specified on the schematic diagram 24 food; the 12-general;